Interconnection Delay and Clock Cycle Selection in High Level Synthesis
نویسندگان
چکیده
This paper presents a method to estimate the delay of interconnections. It uses a simple model based exclusively on point to point interconnections, The method has a very low complexity so it can be used during the clock cycle selection in a High Level Synthesis process. In this way it is possible to settle securely the right electrical behavior of the final circuit
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